1. Field of the Invention
The present invention relates to a driving unit and a display device having the same, and more particularly, to a driving unit having a reduced number of contact electrodes, and a display device having the same, thereby preventing malfunction thereof.
2. Description of the Related Art
Generally, a display device includes a display panel, gate drivers outputting gate signals for driving the display panel, and data drivers outputting data signals to the display panel. The gate and data drivers are integrated circuits, for example, and are affixed to the display panel. However, there is a recent tendency that the gate drivers are formed on the display panel for reducing failure of the display device while affixing the gate driver to the display panel.
FIG. 1 is a layout diagram of a conventional gate driver formed on the display panel. As shown in FIG. 1, the gate driver 10 includes a wiring portion LS delivering control signals from an external device (not shown) and a circuit portion CS outputting gate output signals in response to the control signals of the wiring portion LS. The circuit portion CS has a shift register that includes multiple stages connected one after another and to each other.
The wiring portion LS includes a vertical synchronization start signal wiring STVL, a clock wiring CKVL, a clock-bar wiring CKVBL, and an off voltage wiring VoffL. The wiring portion LS further includes connecting wirings CL for electrically connecting the vertical synchronization start signal wiring STVL, the clock wiring CKVL, the clock-bar wiring CKVBL, and the off voltage wiring VoffL to the circuit portion CS. This configuration causes parasitic capacitances between the connecting wirings CL and the vertical synchronization start signal wiring STVL, the clock wiring CKVL, the clock-bar wiring CKVBL, and the off voltage wiring VoffL, respectively, and therefore a consumed power of the display device is increased. In other words, the consumed power P follows P=f×Cp×ΔV2 (Herein, f is a frequency, Cp is a parasitic capacitance, and ΔV2 is an amplitude of the applied voltage). The parasitic capacitance Cp is proportional to the consumed power, and therefore, the consumed power increases as the parasitic capacitance increases.
Generally, amplitudes of ΔV of the clock and clock-bar signals each supplied from the clock and clock-bar wirings CKVL and CKVBL, respectively, are about 30V. Therefore, the connecting wirings CL electrically connecting the clock and clock-bar wirings CKVL and CKVBL to the circuit portion CS also increase the consumed power P.
Meanwhile, since the connecting wirings CL are formed on a layer different from the vertical synchronization start signal wiring STVL, the clock wiring CKVL, the clock-bar wiring CKVBL, and the off voltage wiring VoffL, each connecting wiring CL is connected to the vertical synchronization start signal wiring STVL, the clock wiring CKVL, the clock-bar wiring CKVBL, and the off voltage wiring VoffL through multiple contact electrodes CE1, CE2, CE3, CE4, CE5, CE6, CE7, CE8, CE9, CE10, CE11 and CE12. This results in eroding the gate drivers 10 at the contact electrodes CE1 to CE12 and therefore causing malfunction of the gate drivers 10.